2014 Abstracts

Panel Discussion

IMAGINE THE FUTURE OF TEST
We're living in a fundamentally different world than we were 10 years ago—or even five. Technology is evolving every day and the techniques that we need to use to test that new technology also need to evolve. Test needs to stay on top of...or more precisely, ahead of...the latest technology trends in order to test the latest devices. Join us for a panel discussion that will be exploring what test may look like in the future, perhaps just five years from now.

DIGITAL

Tips for Successful Pattern Conversion to Eagle DPU16 (12)
There is no pattern file convertor for converting digital pattern files from other testers to the vector format of Eagle Test Systems®. In this paper, the author provides some tips for a successful and easy pattern conversion.

My TF and ATPG Patterns Are Failing: Tips and Tricks to Debug Them (26)
Because the Automatic Test Pattern Generator (ATPG) and Transition Faults (TF) patterns are structural and performance checks disconnected from the end-user device functionality, they leave the test engineer with few means to debug them with traditional device debug approaches. In this paper, the author describes techniques to understand the issues based on pattern behavior (including broken scan chain, discrete fail cells, pattern instability), an efficient way to inform the design teams about the problems, and Design For Test (DFT) and test iterations to achieve expected coverage. These techniques are based on different debug scenarios met in the field and are not test platform/software dependent.

Effect of Training Data Variations on the CDR Lock Time (29)
To achieve data rates more efficiently, the SB6G's CDR algorithms for data rates using MPV 2, MPV 3 and MPV 4 were changed in IG-XL V6.30.00. However, the new algorithms require longer training time. In this paper, the author describes how the variations in training data affect CDR lock time. In an IG-XL migration from V6.20.00 to V8.00.00, a periodic series of five 1s and five 0s were used as the training and testing vectors. The test begins to fail intermittently; all the failures are at the transitions which indicate that the CDR lock time has not been discovered. Different sets of training vectors with more transitions are tried. As a result, the test passes using training vectors with three 1s and three 0s and below while maintaining the same set of testing vectors. Based on this result, a conclusion can be drawn that the CDR lock time for the SB6G does not depend only on the training time but also on the variations in the training data.

System Level Test Using Protocol Aware ATE (33)
As today’s SOC devices become more complex, a real need has emerged for a system-level type of production test to augment existing structural and parametric tests. In this paper, the author discusses how system-level tests can be implemented using an UltraFLEX protocol aware (PA) tester. Existing device features like embedded microprocessors can facilitate such tests and control the test flow through the different blocks and peripherals. The PA features of the tester are used to connect the device interfaces seamlessly in their native protocol to the tester ports. Empirical data show the benefits of this additional level of testing in a production environment.

High Speed Digital Programming Techniques by Differential Measurement (36)
The differential measurement is an optimal technique to obtain better performance when testing a high-speed digital device. Unlike the single-end measurement which needs a clear, large swing and nearly perfect waveform, the differential measurement can achieve good results even from a nasty waveform. In this paper, the author describes how to program some general test items for high-speed digital devices with differential measurements. These applications include how to carry out frequency, jitter and eye measurements for devices with differential pins. Examples from real devices are provided for each test item.

Measuring Switching Characteristics With or Without QTMU? (38)
Measuring switching characteristics in a range of several (or even few) nanoseconds can often become a challenge as the test results get very close to the timing accuracy of the measurement instruments. In this paper, the authors discuss an evaluation study performed on the ETS-88® with the traditional QTMU measurement technique and an alternative method based on receiver-edge placement of DPU-16. Based on the successful implementation of a pre-release setup, comparison analyses between these two methods show significant advantages of the edge-placement method's applications. The study focused on such factors as: accuracy and repeatability of the measurement instrument, test time optimization, parallelism and multisite capabilities.

High Speed and Multi-Lane Testing Using XD Module (46)
The XD Module can carry out high frequency serial testing over 10.7Gbps. In this paper, the author describes how to use the XD Module for testing multi-lane and high-speed devices. A description of how to calibrate multi-lane devices is also included.

UltraSerial10G, Jitter and Eye Analysis Over the 10.7Gbps (47)
While the UltraSerial10G has a 10.7 Gbps limit for jitter and eye analysis, it can have a higher frequency bandwidth in its receiver. In this paper, the authors describe a new DSP algorithm for measuring jitter in the UltraSerial10G over 10.7 Gbps and how they obtained 12.5 Gbps jitter data from the XD source module.

Protocol Memory Display (49)
Loading a huge number of Protocol Aware (PA) modules can lead to memory allocation errors and production stoppage. Oftentimes, users are not aware of the allocated PA memory and space available for loading these modules without issues. In IG-XL, there is no user-friendly provision to view the allocated and available PA memory for a given port/module without impacting performance. In this paper, the authors describe Protocol Memory Display, a technique and tool that allows end users to view the PA memory size with API calls that retrieve the required allocated and available PA memory information for a selected port/module without impacting performance.

nWire PA Makes Digital Source/Capture More Efficient for Various Protocols on Smartphone Baseband IC (50)
With the complex and powerful smartphone baseband IC and more devices being integrated into the baseband package, there are more items to add to the ATE test flow. Some of these items require testing multiple modules and interfaces between device and application circuits. nWire Protocol Aware (PA) in the UltraFLEX can be used to test all types of digital interfaces in the development and debug phases. It can develop code efficiently, debug programs easily and fine-tune production simply. In this paper, the authors describe how they successfully leveraged nWire PA to define various protocols to source/capture data from the register through HOST-UART, SPI interface and tested DigRF and Flash communications.

A New 28Gbps Driver Extension Module for the UltraSerial10G (52)
In this paper, the author describes a new four-channel high-speed serial driver extension for the UltraFLEX UltraSerial10G. This module provides four channels running at data rates from 16 to 28Gbps with programmable drive levels, jitter injection, PRBS and functional data patterns, programmable duty cycle distortion and DC testing with the driver extension in place. This small, low power module fits in the application space on the bottom of the UltraFLEX DIB. Performance data and examples of use are included.

Tips on Using the nWire Engine to Generate Free-Running Clocks for Multisite Applications (63)
Generating a free-running clock with nWire is a feature of the UltraPin1600. Applying it to fan out to reference clocks for multisite applications saves the cost of DIB fabrication. In this paper, the authors describe how to implement a free-running clock with nWire and integrate it into the test program as well as how use nWire to evaluate device performance with characterization.

Synchronization of UltraPin800 and SB6G for JTAG Test of JESD High Speed Serial I/Os (66)
JTAG is an industry standard boundary scan method. For high speed products with JTAG on all digital I/Os, including both non-JESD and JESD pins, the ATPG JTAG pattern needs to be tested using UltraPin800 and SB6G together with vector-to-vector synchronization. JTAG test vectors are typically at a much slower rate than the minimum rate of the SB6G instrument. In this paper, the authors describe a method of pattern creation and instrument synchronization for the SB6G and UltraPin800 pattern, such that both start together at the same point in time and match in frequency to attain vector-to-vector alignment at the slow JTAG speed.

Behavior of the PE Pin When Selecting Input/Output in the Pinmap (70)
In most cases, engineers select the input/output (I/O) type in the Pinmap. However, this selection may cause unexpected problems for some DUTs which can affect the yield. In this paper, the authors describe examples of when these problems occurred and how they learned to prevent them.

Comparing UltraPin1600 HRAM, CMEM and DSSC Digital Capture (72)
Digital capture is one of the most important steps in device testing. In UltraFLEX, there are different methods to capture digital data. In this paper, the authors provide an overview of different digital capture methods on the UltraPin1600 HRAM, CMEM and DSSC and compare their strengths and weaknesses. An example test case using the different methods and describing their performance is also included.

Application of Auto Strobe and DIB Access in J750Ex-HD (74)
In this paper, the author describes how to carry out high precision multipin measurement at low cost. This solution contributes to the improved accuracy of PPMU measurements (from +/- 5mV to +/-1mV). The author also describes how edge searching time was reduced from 0.793208 ms to 0.119627ms with the implementation of a new auto-strobe instead of using the traditional Char tools.

MIPI D-PHY Loopback Relays Can Be Replaced with UltraFLEX UltraPin1600 Passive Loopback Path (89)
Mechanical relays on a DIB are useful for testing loopback for D-PHY, but as the DUT parallel test capacity increased, these relays became an obstacle to increased site count because of the DIB application restriction occupied by the mechanical relays. The UltraFLEX UltraPin1600 passive loopback path can replace the mechanical relays function. The D-PHY TX signal can loopback to the RX pin through UltraPin1600. In this paper, the authors describe how to modify the DIB circuit and code the test program to use UltraPin1600 passive loopback path.

How to Use nWire PA to Implement All BIST Tests for High Speed Devices and Customize a Template for IP Reuse (94)
In this paper, the authors describe a real-life case showing how to use nWire Protocol Aware (PA) to implement all BIST test items for a series of high speed devices using the same intellectual property (IP) core. A register structure was built in VBT based on the IP register map which allows the test engineer to understand and operate the register setting more easily. Customized BIST test templates were created for IP reuse. With these customized templates, the customer was able to transplant all BIST test items in one or two days per project, thereby reducing debug time and achieving shortest time to bin 1. Test time reduction was done simply by recording PA transactions into PA modules. Final test time was almost perfect and beyond customer expectations.

Case Study: A Production Ready Project with Concurrent Test Flow and Massive PA Calls (100)
Some of the new features in IG-XL V8.20.00 make concurrent test much easier to implement in existing test programs. In this paper, the author demonstrates how to leverage the new features into a production-ready program. A demo program is included which is leveraged from UltraPin1600 nWire Protocol Aware which has been available since IG-XL V8.00.01.

How to Optimize High Parallel Digital Test Programs (105)
With the new J750Ex-HD instrumentation, it is now possible to create test programs up to 512 sites. This capability presents new challenges. While site overhead in test time has only a small impact at low site counts (8 sites or fewer), it can result in a big hit in throughput for programs with a very high site count (100 sites and more). In this paper, the author presents a tool that helps to analyze test programs (based on IG-XL test templates), extracting all relevant data out of the test program and combining it with test time profile data. How this data can be used and organized to find areas in the test program which might cause the inefficiency is described. Possible reasons for inefficiency include a poor PTE, wrong approach in the test method and small inefficiencies executed many times.

Rise/Fall Time Measurements on J750Ex-HD (112)
Previously, a characterization algorithm was used to measure rise/time fall times. With the auto-strobe features on the HSD800, rise/fall time measurements can be implemented faster. In this paper, the authors use each approach to compare and contrast rise/fall time measurements. A discussion of theory, requirements and software implementation is included. Results from a quad-site solution of USB rise/fall time will be shared, including scope shots and test time comparisons.

Speeding up Test Programs for High Site Counts on J750Ex-HD (120)
Today, microcontroller products typically run at up to 64 sites at wafer test. The J750Ex-HD has a native IG-XL support for up to 512 sites. At these high site counts, parallel test efficiency (PTE) becomes a much greater focus. While 98.8% PTE might have been just good enough at 64 sites, 256 sites require at least 99.8% PTE. Otherwise, it makes no sense to move to such high site counts. In this paper, the author describes some typical test types and what a test engineer can do to reduce the single site test time and still increase the total PTE using the J750Ex-HD.

The Benefits and Use Model for Concurrent Pattern Testing on the J750Ex-HD (127)
It is not uncommon today for devices to contain multiple die or independent cores that can be tested separately but concurrently. For example, in the microcontroller market, embedded flash memory requires long-running patterns and could benefit from concurrent test of the flash memory in the background while other parts of the device are tested in the foreground. In this paper, the author describes how the concurrent pattern test feature of the J750Ex-HD allows just such a test technique to be easily implemented and programmed as well as the potential test time benefits.

Implementing Sflash Protocol Aware Characterization (132)
While the Sflash nWire Protocol Aware solution has demonstrated improved yield in production with its successful handling of non-determinism data, characterization is another important task to complete the device test program. In this paper, the authors describe how to implement timing characterization for Sflash bus with the nWire solution.

Using DSIO to Measure Frequency on J750 (137)
The J750 digital frequency counter is a good resource for measuring frequency. However, when measuring lower frequencies, the pattern run time must be increased to maintain a good measurement resolution. At lower frequencies, the measurement window must be kept open even longer to get statistically acceptable measurements, which has a negative impact on test time. As a result, the author has developed a method to measure these lower frequencies using DSIO. In this paper, the author describes the method and demonstrates how it is more accurate than the frequency counter while saving test time.

Managing SVM to Improve Test Time (138)
The High Speed Digital 32 (HSD-32) uses two types of memory to manage both the linear and subroutine portion of a digital pattern and the MST software manages this memory for you. With 32 channels in width by 32M (64M) vectors deep in 1X (2X) dual timing, the memory is endless. However, this large amount of memory means the user has to know how to manage the 8K SVM allocation. In this paper, the author describes the rules for optimizing these 8K and successful usage of SVM allowance which drives toward a better test-time. Practical cases to demonstrate how coding a pattern can impact memory usage are included.

Analytical Approach to Loadboard Design (141)
In this paper, the authors describe a process to design an UltraFLEX loadboard as a transmission line to facilitate high data rate I/O testing 5G,10G and higher. S-parameters are used to ascertain this capability for testing SerDes and DDR. This is a direct application of electrical modeling, simulation and verification in the design of an UltraFLEX loadboard. All physical interconnections such as pads, vias, traces and PCB material and components were modeled. Simulations were done to assess the expected performance of the high speed data path. Performance validation of a completely assembled UltraFlLEX loadboard is done through S-parameter measurement using Vector Network Analyzer (VNA).

Testing High Current Switch Devices with Ganging 10 HexVS Supplies (143)
The new requirement for testing high current devices exceeds normal HexVS merged instrument specifications. The DIB ganging technique has been successfully applied to a high current switch device to achieve a higher power supply solution by ganging and merging 10 HexVS instruments together. In this paper, the authors describe and compare the techniques and challenges between VSM and HexVS DIB ganging solutions.

Signal Integrity (150)
When designing a DIB, the selection of circuit material and specification for the signal wiring are important factors. Because signal quality is affected by these factors, it is necessary to know the recommended specification for the DIB design. In this paper, the author describes how to verify the DIB circuit material and the wiring signal pattern for signal quality.

Instructor-Led Online Training (back to top)

TimeLines: An IG-XL Tool for Test Time Reduction (58)
The TimeLines tool, available in eKnowledge, is a standalone graphical user interface that can be used to determine how much time is required to run individual IG-XL test programs. In this paper, the author describes the installation, license and system requirements for TimeLines as well as how to use the TimeLines Viewer to display and compare multiple test time log files. Pareto view, export summary report feature, and two-file comparison improvements new to TimeLines V2.5.0 are also explored.

NOTE: This 90-minute session will be delivered in a classroom at TUG 2014 as an instructor-led online training using remote offline workstations.

Outline

• Introduction
  • System Installation
  • What’s New in in V2.5.0
  • Enabling Timer Markers in Your Test Program
  • TimeLines IG-XL Menu
  • Marker Actions
  • Specifying the Settings (Optional)
• Using the TimeLines Viewer
  • Export
  • Activity Properties Window
  • Quick Mouse Pointer Information
  • Expanding a Code Activity
  • Zoom Control
  • Hiding the Code-Level Activities
  • File Refresh
  • Pareto View
• Multi-File and Comparison Management
  • Changing Displayed File
  • Selecting a BASELINE File for Comparison
  • "Direct" File Comparison
• Future Updates for DSP Profiling and J750 support

Pin Margin Tool & IG-XL V8.20.00 (170)
A Margin differs from the other characterization modes in that it is used to find the range over which a passing test continues to pass. It varies a hardware parameter or spec over a defined range. For each point in the range, it either rebursts the pattern or reruns the test, and records a pass/fail/error for the point. The spec, or hardware parameter, and the tester state are always returned to their original state at the end of a Margin. As well as being run from Characterization Studio, it is also possible to run Quick Margin on one or more specs from a Spec sheet in DataTool. In this paper, the authors describe how to use Quick Margin to margin the specs for the entire flow. Two columns are appended to the Specs sheet indicating the positive and negative margins. It's possible to use default values for the Quick Margin, or you can edit the setup in Characterization Tool, select the specs on the sheet, and run Quick Margin again.

NOTE: This 90-minute session will be delivered in a classroom at TUG 2014 as an instructor-led online training using remote offline workstations.

Outline

• Margin Tool Introduction
• IG-XL Characterization Features
• Characterization Sheet
• Characterization Studio
  • General Tab
  • Test Method (Retest, Pattern Run)
  • Context Tool
  • Create a setup
  • Output Destinations
  • Editing Setups
• Running Characterization
  • Interactive Characterization
  • Flow Sheet Opcode
  • VBT Commands
  • Running Margin
  • Summary

MEMORY (back to top)

How to Implement the Capture Processor on the Nextest MPAC Option to Test a DAC
G Viehmann (23)
The Nextest Magnum testers can optionally be equipped with the Magnum Precision Analog Channel (MPAC) option to support analog test requirements. In this paper, the author addresses how to implement the capture processor feature within the MPAC capture instrument when testing a DAC. The capture processor resides on the capture instrument and calculates real-time INL/DNL during the DAC ramp test. Using the capture processor to calculate the INL/DNL saves test time by not having to transfer the capture waveform for processing. The code required for the capture processor and a description of the test time savings for a 12-bit DAC is presented as well as a discussion about any trade-offs.

Testing 2304 ADCs Concurrently Using The Magnum I Plus MPAC Option Board (51)
Testing 2304 ADCs concurrently can be achieved with the Magnum I's effective modular parallel test architecture with 4-site assembly (SA) boards to test 32 DUTs, each with 72 ADCs, in parallel (8 DUTs per SA) utilizing the Magnum Precision Analog Channel (MPAC) option board to generate the required dual triangular ramp waveforms. This architecture, combined with ingenious self-test code and mixed-signal pattern microcode that allows the simultaneous conversions of 12 ADCs and post analysis of the previously converted 12 ADCs results, enables a successful implementation. In this paper, the authors describe the implementation.

Massively Parallel Parametric Go/No Go Tests with Measured Results Sampling (111)
Reduced pin count devices that allow for testing more devices in parallel, coupled with the need to test parts parametrically, create the issue of wanting to test as fast as possible and still obtain data. On the Magnum 2x and earlier versions, one can use the PTU to test for Go/No Go for all pins in parallel. In this paper, the author takes the next step by suggesting that after running a PTU test, one can then collect measured data for all failing pins and/or sample 16 DUTs in a 1 pin per DUT test program to allow for some parametric data to be stored by using the PMU.

Advanced Shmoo Features on Magnum (116)
The Nextest Magnum product family provides a very powerful shmoo tool with many features. One of the features is callbacks, which allows the test programmer to add processing code for each point on the shmoo. In this paper, the author illustrates an application of shmoo callbacks. The application is for accumulated shmoo, a multi-colored shmoo representing the same shmoo executed on multiple devices.

KGD Memory Testing at 2.133Gbps (117)
As mobile consumer electronics achieve higher levels of integration, the demand for Known Good Die (KGD) in the mobile DRAM market is increasing. The UltraFLEX-M High Performance Memory (HPM) instrument integrated with a new wafer probe interface has the signal performance required to test this new generation of mobile devices. In this paper, the authors describe the wafer probe interface and probe card technology used in this HPM solution and provides waveforms and shmoo plots to demonstrate that this solution can meet high-speed DRAM performance requirements.

Even Parity Subroutines Are Reusable For Your Embedded ARM! (122)
In this paper, the author describes a new technique for hardware parity generation using the Magnum and Magnum 2. This technique consists of a set of generic Magnum pattern subroutines that can generate even or odd parity on the fly and implementing two-way communication using the ARM™ Serial Wire Debug Port (SW-DP) protocol. The subroutine sequences the data to the DUT, allowing the user to deal with the DUT at the register transaction level. Various methods of passing address/data to the subroutine are also described. The patterns provided will run either on Magnum or Magnum 2.

Building Your Own Tester GUI For The ARM Debug Access Port (123)
Magnum software provides handy hooks for building custom GUI tools. In this paper, the author describes an example of an ARM single bi-directional data pin (SWDIO) port debugger which reads/writes to/from an SOC device using ARM SWDIO protocol patterns. An overview of the multi-CPU highly parallel Magnum software is provided and instances of the GUI running on the HOST (Display) vs. Tester (Hardware) CPUs are discussed. Source code, but no ice cream will be provided.

Using TEC Save to Find a Data Valid Window During Synchronous Tests (125)
During synchronous test, not all devices have the same valid data window. Solutions such as running a shmoo on each test or running the devices serially can be time-consuming and costly. In this paper, the authors describe how timing edge comparison (TEC) saves time when looking for a valid data window for each device. The offset can be used for subsequent tests without running another shmoo.

How to Use the Nextest Magnum DBM as a Digital Send Instrument (126)
The digital send instruments in most mixed signal test systems are important in testing DAC devices with sine waves where traditional test vectors are too limiting. In this paper, the author describes a set of APIs that are a software wrapper to the data buffer memory in the Magnum as well as the code and API software implementation for testing a 12-bit DAC with the digital sine wave source.

Memory Testing on IP750 Using Image Processing (151)
CMOS image sensors are easier to implement on system-on-chip than CCD image sensors. In recent years, memory and CMOS image sensors have been mounted on the same die. It is not easy for image sensor test engineers to do memory error analysis with Memory Test Option. In this paper, the author describes a technique of memory error analysis using the image processing installed on the IP750. By transferring error information to the image memory of the tester PC or the image PC, users can do memory error analysis for columns and blocks.

Controlling Voltages in a Pattern on the Nextest Magnum I (152)
Many of the programmable voltages on the Nextest Magnum I can be set or modified from a pattern using the LSENABLE and LEVELSET pattern instructions. In this paper, the authors describe how to control DPS levels and PMU force voltages. The voltages may be hard-coded in the pattern or modified on-the-fly. Examples of each method are provided and the advantages and disadvantages of each are discussed. A comparison of the TWEAK and SET operations is also included.

MIXED SIGNAL (back to top)

Keeping All the Cores Busy - How to Multithread with IG-XL (3)
In IG-XL, it is possible to reduce test time by using threads from VBT to perform operations independent of the main VBA thread. To use threads from VBT, a separate library, usually written in C, C++, or a .NET language, needs to be developed that calls the library functions from VBA code and passes necessary data to the function as input parameters. There are restrictions on what these functions can do. In this paper, the author describes how to use these libraries and the rules that should be followed.

Automated Eagle Wait Time Optimizer and Production Release Tool (8)
Rightfully so, test engineers are concerned with device specification verification more than wait times during test program development. However, it's important to optimize wait times to prevent wasting precious tester resources and increasing parts per hour. In this paper, the author describes the Eagle Test Systems® wait time optimizer, a tool that optimizes and provides user information about wait times. It changes the test program in such a way that two level weightage variables are introduced for each lwait/swait statement and control for these variable is given to the user. All users need to do is load the changed test program on the tester recompile, put the GEC unit in the loadboard socket and loop the program to reduce the wait time. During production, all the code that automates the process of reducing wait time is removed and the program is readied for release. This tool can also optimize wait times for each lot.

Programming Sine and Cosine Waves Using the LMF on J750 (17)
Low-to-Mid Frequency (LMF) for the J750 instrument only supplies LMFSineGenerator; it is quite limited since there is no cosine generator available. In this paper, the author shares his tool for simple sine/cosine wave generator, and also showcases a technique for generating other waveforms.

MATLAB 2 UltraFLEX: A Design Flow for Custom DSP Algorithm Development (27)
UltraFLEX provides a standard library of DSP functions with which test engineers can create analysis routines to cover most use cases. The UltraFLEX also offers the ESA product, which provides complex demodulation and performance analysis of signals conforming to a wide range of wireless standards. Unique analysis functions that are not supported by these standard methods can be addressed with custom DSP algorithms. These algorithms are coded in C++ and imported to the UltraFLEX DSP. In this paper, the author describes a design flow from MATLAB® to UltraFLEX DSP. By accepting MATLAB as source code for custom test DSP functions, design and verification time is reduced. For developing unique DSP algorithms from scratch, MATLAB is the gold standard for accuracy, debug, and visualization, thus also reducing design and verification time.

Multi-Tone Generation on Eagle Test System Arb (39)
In this paper, the authors describe a multi-tone sine wave generation tool that allows an easy method for generating coherent multi-tone waveforms using an AWG instrument. A code example on an Eagle Test System® is presented and performance results shared. Also included is a review of generation debug tools and a measure of actual performance.

DC Trend Removal by DSP-based Analysis on DAC Testing (57)
DAC testing may measure the waveform with a repulsive DC trend offset from the digitizer. It is influenced by the dynamic figure calculation and uses some of the DUT wait time to get the flat noise floor in spectrum; this usually occurs with the DC blocking capacitor in the DUT board. In this paper, the authors describe how to use DSP-based analysis to remove the DC trend offset and exhibit a reasonable spectrum which also reduces the DUT wait time on DAC testing.

Testing Ultra Low-Power WLAN SOC with Protocol Aware (65)
In this paper, the author discusses Protocol Aware (PA) and handshaking methods used to program and test a customer's device. The device utilizes dual-embedded ARM Cortex M3 processors for control. PA is used to program these processors as well as normal register read/writes and embedded ADC/DAC testing via the SPI bus. CPU-to-tester synchronization is also discussed as well as the advantages/disadvantages of PA Record methods and resource mapping to account for general purpose pins.

Encoding and Decoding a Sine Signal for PCS 10base-G 64b66b Standard (71)
UltraSerial10G supports 8b/10b encoding intrinsically. In this paper, the authors introduce a way to leverage UltraSerial10G with existing DSP methods to enable support for 64b/66b encoding and decoding a sine signal for the physical coding sublayer (PCS) standard. They show the working software protocol implementation of IEEE 802.11ae 64b/66b sec. (Clause 49) PCS standard. This standard applies high speed ADC/DAC sample transport in SOC. The implementation of this software subprotocol involved solving the standard XGMII SerDes interface for both RX and TX.

Continuity Probe Solution (73)
This test program and DIB solution are developed as a standalone solution to improve customers' confidence for probe docking performance. In this paper, the author describes a solution that verifies whether there are any continuity issues up to the probe card, highlighting the affected pogo pad as well as the instrument behind it.

High-speed SerDes DAC and ADC Test Solution (82)
For high-speed SerDes DAC and ADC, the UltraPAC80 is used to test the mixed signal parameters. The UltraSerial10G sends high-speed serial signals to the digital ports of the DAC and receives signals on the ADC digital ports. The encoding and decoding algorithms are implemented during SerDes signal delivery. In this paper, the authors describe this test solution as well as a test technique for basic high-speed SerDes parameters such as TJ, rise time and fall time. The UltraPin1600 source sync technology which addresses the challenge of the unpredictable ADC data output is also described.

Automated Printing of Test Resource Condition in Eagle Tester Without Using RAIDE (88)
In this paper, the author details a function which can print out Eagle Test Systems test resource conditions without using RAIDE. The function will print out the test resource at each point the function was called and export it into Excel®. It is no longer necessary to stop the test program and use RAIDE to print out the test condition. One more application is finding test conditions at test points where the test program cannot be stopped due to reasons like high current, especially during debug. This script is being used by multiple test engineering teams and can be used for program quality check during releases.

How to Avoid Yield Loss Due to Site-to-Site Interaction Caused by Substrate Currents (101)
Site-to-site interaction caused by substrate-currents during multisite wafer sort test can cause unnecessary yield loss. In this paper, the author discusses the most common site-to-site interaction issues, methods to detect them and their possible solutions. Special attention is given to interaction that is only seen at the DPAT stage of the wafer test flow, a means to discover tests susceptible to this kind of interaction and how to prevent these tests from negatively impacting yield and cost of test.

HDCTO vs. MSO – Emerging Competition in the AC/Mixed Signal League (102)
The new High-Density Converter Test Option (HDCTO) extends the J750 instrument family by a high channel count analog member. Its architecture provides solid AC/mixed signal capabilities which were an exclusive domain of the Mixed Signal Option (MSO). In this paper, the author shows how the HDCTO performs, analyzing areas where it can replace the MSO to allow higher parallelism and where the limitations are. Ways to program the instrument for these tests along with a collection of handy code examples are included as well as a discussion of concepts for differential and negative signals.

Adaptive ETS Resources Application (106)
In this paper, the author introduces an assistant code template which helps the coherent sampling condition setting based on Eagle Test Systems (ETS) specifications and provides a warning about FFT non-periodic leakage. The template analyzes captured signals and displays the perfect coherent condition for them. Based on previously analyzed information, activating the auto coherent sampling mode changes the template sampling condition automatically. There is also an easy-to-use code library that can be connected to the ETS spectrum function. The correlation to UltraFLEX IG-XL DSP calculation results is also described.

Data Converter Test Considering FFT Process Gain (114)
There are a wide variety of tests for measuring data converter performance. Many testers provide analog source and digital capture memory for storing the Fast Fourier Transform (FFT) results which are strongly correlated to coherent sampling and sample numbers. The noise floor of the FFT spectrum is from quantization. For an M-point FFT, the average value of the noise contained in each frequency bin is 10 log2(M=2) dB below the rms value of the quantization noise. FFT process gain is why the noise floor appears 30 dB lower than the quantization noise level. In this paper, the author introduces a test method for FFT process gain. This method can provide a fast and cost-effective data converter test solution through a simple Pset and capture memory modification.

Mixed Signal ADC Testing with the UltraVI80 Instrument (130)
Use of the UltraVI80 instrument an arbitrary waveform generator was put to the test, literally, for a customer's successive approximation analog-to-digital converter (ADC) and sigma delta ADC. In this paper, the authors describe programming solutions for ramp and sine waveforms, share methods to snoop the resulting waves with the DCDiffmeter and present final results for multiple frequencies of interest.

Implementing Concurrent Test on a Mixed Signal Device (136)
The Intelligent Distributed Control applications are a solution for relay-driven applications that combines two different dies in a single package. Both dies communicate through a Die-to-Die interface (D2D). The D2D-controlled analog die combines system base chip and application specific functions. From the DUT side, each die has own test port. The D2D interconnection can be set to HiZ mode for isolation, making it ready for concurrent testing. In this paper, the author describes how to execute concurrent test using a single package solution, showing a test time savings of 40% over non-concurrent testing.

Rotating Gravity - Frequency Domain Test for MEMS (145)
MEMS, or Micro-Electro-Mechanical Systems, sense real-world physical stimuli and convert the physical signals to electrical (mainly digital) signals. Accelerometers (sensing linear acceleration) and Gyros (sensing rotation) are two of the most common types of MEMS sensors. Multi-axis accelerometers, gyros and other sensor types are routinely combined into single devices. A multi-axis combined accelerometer and gyro MEMS device is tested efficiently and thoroughly by utilizing uniform circular motion in gravity as the input stimulus. In this paper, the author describes how frequency-domain test analysis, familiar to mixed signal test engineers, is utilized to measure the MEMS sensor response. The uniform circular motion is sensed simultaneously on all axes, and cross-axis response can also be measured.

POWER MANAGEMENT / AUTOMOTIVE (back to top)

High-Voltage Detect Tool to Avoid HSD Gripen Circuit Damage (10)
Engineers may face situations where voltage was discharged on a DUT pin which is connected to a DCVI via a large bulk capacitance. The DUT pin can have an HSD and another instrument (usually a DCVI) connected without a relay, or the DUT pin can have an HSD channel connected to another instrument (DCVI or HVD) via a capacitor. If the discharge time is not long enough, there may be some voltage remaining on the DUT pin. If a programming mistake occurs when the DCVI or HVPMU is connected at the same time that the DUT pin is connected to the HSD channel or PPMU, it will damage the HSD Gripen circuit. In this paper, the author describes a high-voltage detection tool that can avoid HSD Gripen circuit damage.

PVI for Power/Automotive Testing: Optimizing Test for Production Environment (16)
PVI is an external high power instrument/module for the FLEX family of test systems. In this paper, the authors introduce how this instrument is used in some of the automotive/power application tests. Next, the authors describe how important it is to program the PVI settings with special considerations for power dissipation during the device shutdown testing condition.

High Accuracy Wafer Level RDS(on) Measurement Techniques (31)
New packaging solutions have made multi-die products practical which increases the need for known good die and improved test quality at the wafer level. In this paper, the author describes three major challenges associated with high accuracy high current wafer level RDS(on) testing: potential Source needle damage due to high contact resistance, Source sense voltage error due to variations in contact resistance, and Drain voltage sense error due to limitations related to chuck sensing. Innovative test techniques are presented that address each challenge area making it possible to test sub milliohm RDS(on) products in production.

Terminating Toxic Test (32)
In this paper, the author introduces technology within the ETS-800® that helps avoid tester damage due to hot switching. The ETS-800 incorporates a relay switching control process that largely prevents users from causing many types of hot switch events while maintaining high execution speed. The merits of solid state and reed relays and their potential impact on test system performance are compared and contrasted. In addition, a number of common application cases where hot switching may occur will be presented and analyzed.

96V Automotive Testing Using APU12: Trials and Tribulations (42)
Higher voltage testing is becoming more common as we push into industrial and automotive markets. To support that need, clever applications of existing tester configurations are needed. If a tester configuration has eight SPU100 channels, that configuration is limited when a lot of channels are needed above 30V. The solution is to leverage the APU12 resource and start stacking. To do this safely and stretch the 30V limits, both the hardware and software solutions need to be designed carefully. In this paper, the author presents lessons learned and best practices in the context of developing a 96V automotive test solution.

Advanced APU Measurement Techniques (53)
In this paper, the author discusses different techniques/DIB circuits that can be utilized to increase the performance of the APU. In part one of this three-part paper, the author describes a DIB circuit that can facilitate the use of the APU for making differential measurements with micro-volt accuracy. A simple technique for doing a fine-adjust of the forcing voltage of the APU to provide a very accurate reference voltage is described in part two. The final portion of the presentation discusses a unique feature of the APU-32 which facilitates faster settling times during low leakage measurements with the presence of a capacitive load.

Site Control Across Sectors with MST (54)
Eagle Test Systems MST software allows a test program to be run in Multi-Site Distributed (MSD) mode, which yields extremely high multisite efficiency. However, using MSD adds a layer of complexity when it comes to individual site control. In this paper, the author reviews some of the various scenarios that a program may run into and how MST handles each situation. Examples include turning sites on/off across distributions, trimming, focus calibration, and reading and writing to files.

Taking Full Advantage of ETS-800 APEx Architecture (60)
The ETS-800™ offers a unique set of internal matrixes that allow for very fast, safe resource sharing. This architecture is known as APEx (Adaptive Pin Expansion). The ETS-800 was designed from the ground up to make the most efficient use of all resources in the testhead, while eliminating the need for DIB relays. It allows for per pin VI, while reducing the number of higher performance resources needed to test complex PMIC devices. In this paper, the author shares some best practices for using APEx and describes many of its advantages.

Testing Power Modules and Smart Power Modules with New ETS Test System (68)
Power modules are high-power capable semiconductor devices used for controlling high-power consumer and industrial applications for energy efficient systems such as aircons and electric vehicles. Low voltage ICs were paired with these high-power modules in a single package to interface with MCUs for intelligent control, thereby creating a new family of devices dubbed Smart Power Modules (SPM®) or Intelligent Power Modules (IPM®). For this application, the new ETS system was developed to address the requirements of testing these high-power devices. In this paper, the author describes the test methodology for testing high-current and high-voltage power modules and SPMs with this new tester from Eagle Test Systems.

Challenges of Mobile PMIC Device Testing on ETS-800 with Direct Probe I/F (86)
Teradyne engineers in Korea responded to a customer request for information about the performance and usefulness of the ETS-800®, a new PMIC test system from Eagle Test Systems. The customer not only wanted to know how well the new tester performs, but also how they would use the direct probe interface for PMIC testing. In this paper, the author describes how the conversion from the ETS-600 three-sites test solution to the ETS-800 eight-sites test solution resulted in 33% faster test time and provided good correlation data that also correlated with the ETS-600. Efforts to reduce test time further continue.

Test Quality Improvement for Automotive Products (91)
In the automotive market, product quality is essential and test program quality has a key stake in the process. While the semiconductor industry made huge strides in developing DFT and other methodologies to maximize fault coverage, the effort did not lead to high quality, exhaustive automated solutions. In this paper, the authors describe an innovative enhancement that combines three elements in the test development process to measure test coverage effectively. They are: 1) automated traceability of test requirements; 2) heuristic analysis of the test program; and 3) validation of test results respective requirements. Evidence of experimental results and utilization examples on the J750 are included.

Need more time? Follow the fat rabbit! A Way to Spot and Eliminate Time-Wasting Code in Eagle EV & MST Test Programs (96)
Test time reduction is made easier and more streamlined with the right tools and knowledge. Using a commercial profiling tool to collect execution times of all statements efficiently within a single test program run will set the base to tackle inefficient code quickly. In this paper, the author discusses how data analysis can be taken offline, freeing up valuable system time and enabling collaboration. Exporting the data into Excel® makes hunting the "fat rabbits" a pleasure! Once identified, following a few golden rules, test time optimization can be an efficient and structured approach.

Test Time Reduction: Our Story (115)
In this paper, the authors describe the different paths and methods they used to reduce test time to 20 seconds from more than 60 seconds. Their process covers the time from test program development to release in production. A description of how they leveraged the new tool sets available on the IG-XL platforms to achieve this reduction in test time is also included.

Simple Method to Generate Transients of >30KV/us Using the SPU500 (135)
All electronic devices in industrial and automotive systems must be compliant with a minimum Common Mode Transient Immunity level. We must ensure that the integrity of digital signals is not compromised by the operation of electrical motors. In this paper, the author describes a simple and easy method to generate transients with slew rates >30 KV/us by using the SPU500 and an on-board circuitry that can be triggered by either the DPU16 or APU12. The amplitude of the transients can be set up to ±500V by using a single SPU500, or up to ±1KV when using two SPU500s. Oscilloscope signals are shown as well as their applications for production tests.

Understanding Index Parallel Testing (144)
Under certain conditions, index parallel testing can provide significant test time advantages when using rotary or inline handlers. It is important to understand what these advantages are and when they outweigh the issues involved with index parallel testing. In this paper, the author explains when it makes sense to use the index parallel method and the unique requirements of the test cell when using index parallel.

Best Practices and Test Techniques with UPU-64 on ETS-800 (146)
The UPU-64 is a 64-channel utility pin unit that facilitates optimal tester resource usage efficiency (TRUE). It contains a dual 2x8 force/sense matrix, per-pin PMU, high voltage digital, wrap back capability, and per-pin access to 16 shared time stampers. In this paper, the author introduces the instrument to new users and demonstrates best practices and test techniques.

Time Measurement of Real-World Signals (147)
Real-world waveforms are susceptible to noise and reflections which can make time measurements challenging. In this paper, the author describes methods for overcoming these challenges using the ETS-800 system features.

SPU-112 SOA Characterization (153)
In this paper, the authors discuss issues associated with the characterization of the SPU-112 Safe Operating Area (SOA). Also examined are general power delivery issues, common to all power V/Is. On one level, SOA characterization can be approached as a power problem, with delivered power measured in Watts (P=V*I). However, depending on the current, voltage and pulse width/duty cycles of the delivered power, different areas of the V/I instrument can reach their operating limits. The SOA curves themselves reflect internal V/I limitations on heat dissipation and recharge capability. A framework for analysis of these capabilities/limitations is discussed based on a simplified use model. And, real-world characterization data are presented. Also discussed are the practical recommendations for users to estimate the affects of and limitations on more complex pulsed waveforms.

APU-12 Best Practices (154)
In this paper, the authors discuss a set of recommendations and guidelines that minimize the likelihood of damaging an APU-12 under normal, production use conditions. The APU-12 has practical limitations, based on circuit design, in terms of the voltages and current that it can tolerate without damage. Common issues include exposing the resource to voltages outside its safe operating range, hot switching of the output relays, and improper control of other V/Is when used in a stacked configuration. Drawing on real-world examples, applications situations are described as well as a discussion of best practices techniques. In addition to reviewing the basic operating range and capabilities of the APU-12, specific rules and practical guidelines for use in test program development are presented.

RF WIRELESS (back to top)

TD-SCDMA Demodulation and EVM (15)
Time Division-Synchronous Code Division Multiple Access (TD-SCDMA) is a 3G cellular standard that is primarily used in China. Error Vector Magnitude (EVM) is a common measure of transmitter modulator and receiver (Rx) demodulator quality for communications standards such as TD-SCDMA. In this paper, the author details the process of demodulating a TD-SCDMA signal and calculating the EVM measurement. Extensive use of the DSPVector library and frequency-domain duals of sample rate conversion and signal correlation are implemented for dramatic reductions in calculation time.

Dynamic Error Vector Magnitude (DEVM) Test for RF Power Amplifiers (PA) and Front-End-Modules (FEM) on the ETS-88 RF (19)
In this paper, the author defines and demonstrates Dynamic Error Vector Magnitude (DEVM) measurement technique on the ETS-88® RF test platform. DEVM is a key test to ensure quality for RF power amplifiers and front-end modules (FEM). The ETS-88 RF test platform utilizes synchronized RF source and measurement capability to perform this test. A description of the setup and how to perform the DEVM measurement as well as an interpretation of DEVM results are included. The example RF device is a Wireless LAN FEM.

Low Cost RF SOC Solution with J750Ex-HD+LitePoint RF (24)
More and more, baseband devices are embedded in RF blocks to reduce the cost of mobile phones. The old generation ATEs are unable to support high volume/low cost production and cannot test all the new RF features. In this paper, the authors describe a qual-site RF SOC solution on the J750-HD with LitePoint boxes which enable the simple RF capability to the J750, extending the life of the largest install-base tester in the world.

Test Optimization For Dual RX RF Transceiver (25)
In this paper, the author describes how to test dual receive paths in parallel to achieve the shortest test time. The target device contains two independent receive channels. In this single conversion system, two LOs are required to provide the frequencies that generate the quadrature signals for the two separate receive paths. A significant amount of test time is needed to test the two receive channels separately. However, carefully positioning the LOs at the high side/low side injection helps to test the dual receive paths in parallel. Setting the LOs equidistantly to the RF input may save 65% of the overall test time, a finding useful for testing devices with multiple receive/transmit paths.

LTE-A Test Time Reduction with UltraWave 12G (Modulation/Demodulation) (28)
For LTE-Advanced device development, the DC offset, IQ phase error and some other calibration processes increase test time because they are serially implemented for each site. In this paper, the author describes how using the UltraWave 12G receiver block, POP and hardware DFT can reduce test time by 20% to 30%. A discussion of the full functionality of the UltraWave 12G is also included.

SerDes Testing Beyond 15GBps (30)
Many of the newest electronic products use high-speed serial links, such as SATA, PCI-Express or SerDes, instead of a parallel bus. The current installed base of older generation testers like the Catalyst or microFLEX is not capable of testing these new, high speed serial links. Even newer testers may not be able to test serial links at the current rates of 25 Gbps. In this paper, the authors describe how using an upgrade, which contains a 4-channel BER generator, DSO and BER receiver, will allow these testers to test high speed serial links.

Probe Card Design Guidelines for Test Concurrency on RF Connectivity Devices (37)
As the cost of test increases, so does the demand for alternative testing solutions. Teradyne has introduced an effective test solution that increases test throughput (lower cost of test) while maintaining equal test coverage. In this paper, the authors describe some hardware design guidelines for test concurrency using the UltraProbe solution on connectivity RF devices.

Measuring Noise Figure for RF Receivers Using UltraFLEX UltraWave12G Receivers (43)
Noise figure measurement is an important test for RF receivers because the input RF signal can be small and weak. This test is to decide how much noise the DUT adds. A high noise figure limits the device's ability to process its incoming signals. The testing challenge is to eliminate the noise contributed by DIB components and the UltraWave12G receiver. In this paper, the authors evaluate both the Y-factor and Gain method and compare correlation results with bench tests. Their study is based on a microwave backhaul receiver with input frequencies that are up to 20GHz while output is down converted to baseband frequencies.

Testing Wideband IQ Signals Using UltraFLEX UltraWave 12G Receiver (44)
Microwave devices are a niche market. Although the volume is relatively low compared to other consumer wireless markets, microwave devices are important in the communication system, including the need for them in satellite communication and cellular base stations. Usually, the bandwidth of a microwave device is much wider than in consumer wireless devices. Its baseband bandwidth level is close to 1GHz. Because of its wide bandwidth, the baseband signal needs to be treated as "RF" at some points. Today’s UltraPAC80 cannot support wideband IQ signals. In this paper, the authors provide a real-life example of how to test the wideband IQ signals on UltraWave12G.

Reducing EVM Error Through Traditional Device Calibration and Error Correction by ESA for LTE Transceivers (97)
Increasing quantities of data drive higher data rates which drive higher accuracy requirements in devices. This increases constellation density which decreases the room available for error vector magnitude (EVM). In this paper, the authors describe the relationship between an EVM error and device calibrations such as image rejection (IRR) and carrier feed through (CFT). In addition, a description and comparison of how to reduce EVM errors through device calibration and with error correction methods such as the ESA Toolkit are included.

LTE-A Transceiver Quad Sites Test by Daughter Board on UltraFLEX (98)
Because of its multiple-input and multiple-output functionality, the LTE-A device has nearly twice the RF ports of the LTE. Therefore, it is not only difficult to make loadboards, but the possibility of spoiling the loadboard increases when trying to match RF ports that have lost pattern through soldering. A daughter board scheme can correlate data between the bench result and ATE which helps reduce verifying and correlation time as well as the risk of a spoiled loadboard. In this paper, the authors describe the benefits of a daughter board scheme and how matching and repairing the spoiled loadboard during production can reduce costs and increase time to market.

Multisite RF Probe on the J750 (118)
In general, wafer test is defined as having a large digital component and a small-to-zero RF component. One reason for this definition is that most probe ATEs do not have RF instrumentation installed. In this paper, the authors describe a way around this issue by using a J750 and custom-designed RF modules. These modules, which are driven by the J750, are then used to source and capture RF signals up to 1GHz. How this solution is viable for parallelism up to 16 sites is also described.

RF Performance in Array Structures Based on Ground Placement (121)
In this paper, the authors describe the effects of ground placement relative to the RF signal or signals in an array structure, including data on how the test fixture used to test these devices (e.g., BGA or WLCSP) is impacted by the location and number of grounds, such as GSG and GSSG. Since the IC industry is moving to smaller pitches with more integrated devices and higher I/O counts, the effects of pitch on devices in terms of RF performance are also described as they all factor into the performance of the device on the circuit board and in the contactor during testing.

Using the nWire DUT Clock to Capture Highly Unstable Device Clocked Data (131)
In this paper, the author describes an application where nWire Protocol Aware captures data referenced to a highly unstable device-sourced clock and is clocked on both rising and falling clock edges. Resource assignment and DIB and program design considerations to scale the program from a single-site engineering program to a 16-site wafer sort program are also included.

Get the Most Out of Those RF Ports You Have! (166)
With device RF port count increasing dramatically as new standards, frequency bands, carrier aggregation, and MIMO are introduced, the challenge for the test engineer is to continue to reduce cost of test while testing these complicated devices. This is primarily achieved through higher site counts and reduced test times to increase throughput. The key to achieving this goal is identifying the true minimum configuration required to test a device while maintaining a device limited test time and not sacrificing yield. In this paper, the author shows how to optimize RF port assignments to enable higher site counts without sacrificing test time, PTE, or yield.

Testing RFIC Devices Over DigRF v4 (168)
DigRF v4 is the latest version of an industry standard interface primarily used between RF transceivers and BBIC devices. This version allows support for Long Term Evolution (LTE) and Mobile WiMax along with 2.5G and 3.5G cellular technologies. In this paper, the authors describe the test challenges and how the UltraFLEX can provide a high throughput solution.

What Do Higher Data Rates Mean to Cellular and Connectivity Testing? (169)
Today's cellular and connectivity devices are achieving higher data rates by various means like MIMO, diversity, aggregation and higher bandwidths. Each of these approaches presents challenges to test. In this paper, the author will present an overview of the standards that use these techniques, describing why they use them and how they can be tested.

Effect of DC Supplies on RF Transient Response (171)
RF tests, such as dynamic error vector magnitude and transient mode switching, that focus on the transient response of RF power amplifiers can often be affected by the DC supplies used to power up the DUT. In this paper, the authors describe how adding capacitance to the supply pins on the DIB can help overcome issues resulting from DC supplies that cannot react quickly enough to changes in DUT current demand. The negative affect increased bypass capacitance has on common tests such as Leakage is discussed, along with proposing some simple solutions to help mitigate these effects.

UltraWave24: The Future of RF Test (172)
Teradyne is releasing its next generation RF instrument. In this paper, the author highlights the new features, improvements and increased port count as well as providing a detailed overview of the architecture. Some of the new features are described, including higher port count, bandwidth to support all 802.11ac and LTE-Advanced standards, and improvements for concurrent testing, is included.

ESA Programming Overview & Test Time Reduction Methods (173)
This tutorial provides an overview of ESA programming methods and how to optimize the ESA toolkit. It also describes how to prepare a modulated test using ATE with a focus on how to determine the required bandwidth and instrument selection that satisfies the modulation test requirements.

TEST INFRASTRUCTURE & PRODUCTION (back to top)

IG-Link: Stop Merging and Start Linking (1)
Modern ICs are created with many modules designed by separate groups; they are tested with very large test programs and managed by teams working on separate parts at a time. In previous years, many individual solutions have been created to load subsets of a test program. IG-Link offers a novel approach to enable collaborative development relying on linking test programs instead of merging them. IG-Link is extensible, allowing users to add plug-ins, such as program generators. In this paper, the authors describe IG-XL program modularity, IG-Link capabilities, limitations and examples, as well as how to extend IG-Link.

IG-Diff - You changed what? (2)
Until today, the only tools available to IG-XL developers for comparing versions of a test program were the standard compare tools. These standard tools indicate which files have changed, but provide no insight into which tests in the program were impacted by those changes. The IG-Diff tool provides those insights, allowing you to compare two versions of a test program to determine which tests are different and the sources of the differences. In this paper, the authors describe the IG-Diff tool and how it can help with collaborative development and test program change audits that will result in a higher quality test program.

IG-Data/IG-Review – What's in these 200 sheets anyway? (4)
IG-Data enables a client to read in and gather information from an IG-XL test program. It stores the test program data in .NET objects and provides a .NET class library to allow the client to query the data. IG-Review will be used as an example data client that reads in an IG-XL test program and produces reports that will aid the test engineer during code reviews, helping to ensure that only quality test programs are being released to production. Anything that exists in the sheets can be reported against. In this paper, the authors describe IG-Review and how to use it for simple reports such as conditionally run tests and missing bin numbers.

ETS-364 Eagle Vision/ETS-88-MST/ETS-800-MST Upgrade Process for Windows 7 Offline Systems (5)
Support for multiple operating systems (OS), licenses and compatibility has been impacted by the Windows® 7 upgrade in many companies. Since Eagle Vision® was developed on the Windows XP OS to support older Microsoft™ Visual Studio® software tools for test solutions, this upgrade could be a major roadblock for product release to customers. In many cases, it was in the critical path of the new product development cycle. In this paper, the author describes a streamlined process that allows users to speed up the upgrade, saving hours of troubleshooting various software setup issues including compatibility between Windows XP and Windows 7.

High Site Count Test Solution Using 10K Probe Tower (13)
The release of high-density instruments on the UltraFLEX for both digital and power has enabled customers to increase parallelism in probe solutions. However, the current probe tower is not sufficient to cover a fully configured set of high-density instrument channels. This configuration drives probe tower needs beyond all existing solutions available today. In this paper, the author describes mechanical and electrical details of the high pin count 10K Probe Tower as well as introducing a successful implementation of a prober docking solution for the UltraFLEX. The author also introduces the probe card debug tool which allows a probe card to be installed on the test head without docking it to a prober. A table comparing the existing probe tower and new 10K Probe Tower is included as well.

Dynamic Test Sequence Control in Eagle Test Systems Product Sheets (18)
Adding a flow module into an existing PDS in an Eagle Test Systems® tester provides additional flow control overlaid onto the core program for non-production uses. This module reuses the existing test modules/conditions already in the PDS and overwrites test conditions/limits from a text file containing start/stop ranges for inputs and stepped test limits. Changes can be made to the text file for non-default conditions, limits and loop counters, but the core program remains unmodified. In this paper, the author describes several ways to use this flow module, including optimizing trimming operations over a range of loads/supply voltages and regulation modes conditional branching for special screens based on bin ranges.

Test Time Analysis and Multisite Efficiency Made Easy (41)
Using simple VB and scripts (PERL and R), users can extract datalogged test times and site information from STDFs and generate accurate test time profile reports. These reports calculate x1 test time and tester multisite efficiency, predict test times for various multisite configurations, and generate other statistical measures in less than one minute. The test time data are generated on a per test module as well as complete program basis. A generated HTML table allows users to compare results easily between different test programs and parts. In this paper, the author describes how engineers can focus more time on fixing inefficient/poorly written modules/tests and less time collecting, sorting, and analyzing test times with this data.

100X Faster ASCII Worksheet Import in Excel (45)
ASCII is the gold standard for configuration management of IG-XL worksheet data. As test programs grow in size and Teradyne moves more data into worksheets, ASCII import time is increasing and slowing down test engineering productivity. Teradyne supports ASCII import and export of Excel® worksheets in Datatool as well as the applications engineering-supported ASCII Utils tool. In this paper, the author reviews the current methods and presents a new method than can speed up ASCII import in Excel dramatically.

PCB Integrated Solution for IC Testing (59)
In this paper, the author describes a printed circuit board (PCB) integrated solution to improve IC testing time in production developed by the Teradyne Taiwan team. This solution, which is a design and turnkey service for DIBs, would be particularly helpful to customers in Asia, especially in the Greater China area. Topics to be covered include a description of PCB design, simulation, module design, manufacturing and assembly; an integration solution with socket and probe head; flying probe test; and troubleshooting tips.

New Instrument Customer Evaluation (NICE) Flow (62)
Making sure a new instrument meets customers' needs goes beyond running a set of diagnostics and looping for stability. It must also perform in an actual test application with the least amount of investment of money and man power. In this paper, the authors describe how this qualification requirement was met for the High Density Pin Measurement Unit (HDPMU) instrument at a customer site. A detailed flow is also proposed for future instrument evaluations and detailed data presented for the HDPMU qualification.

Resolving Encryption Issues with Teradyne's Test Program Protection Tool (64)
Teradyne's Test Program Protection Tool was used to address a customer's program encryption request. Initially, the tool could not encrypt the program because the customer did not want to encrypt the patterns (the patterns were too large and it would take too much time to encrypt them). In addition, the workbook name needed to be changed. The Test Program Protection Tool only accepts exported ASCII files and cannot keep the workbook name. After Factory Apps provided a patch enabling encryption, the request could be met successfully. In this paper, the authors describe the issues they faced and their resolution.

Probe Card Supernova! Best Practices and Lessons Learned to Avoid Burnt Needles (67)
During test program development for wafer probe, one common problem is a damaged probe card, which can increase the cost and cycle time for production release. In this paper, the authors examine the steps from designing the probe card to coding the high current tests to ensure that there won't be probe card issues or burnt needles during program development and production. A description of the lessons learned is included as well as a test technique to avoid high-starting static currents.

Automating Flow Simulation (75)
Test programs for highly integrated complex SOCs may be divided into sub-flows and the flows are often highly complex structures incorporating conditional branching. The fact that the test programs are usually multisite adds another dimension of complexity. In many cases, complex binning may be implemented. Ensuring that mistakes are not made in the flow and binning logic can be a significant challenge as well as the verification process which can be tedious and time-consuming. IG-XL provides a number of tools and features to assist the programmer, but the simulation requires the user to set the result for each test and site manually. Going through every combination of test failure to verify the integrity of the flow and binning logic can take time. In this paper, the author describes a way to automate flow simulation to speed up the verification process.

Online Stability Study Tool (79)
In this paper, the authors describe a tool that reduces the time to evaluate test results from a stability and correlation point of view. It displays statistical measurement results online in real time which enables the test engineer to take corrective action immediately. The tool is also useful in tracing correlation issues between the DUT sites because it can present the results of all sites of a particular test together, again allowing for immediate evaluation.

A Study on Optimized Settling Time and Device Interface Board Application for Measuring Static Power Dissipation of the Device with Large Capacitor Applications (80)
Static current value of the power pin is usually used to estimate or calculate the static power dissipation. Under test conditions, a capacitor application is usually essential for power pins in the device interface board (DIB) design. Because of these capacitor applications, the traditional method of measuring the static current requires adding relays to match the number of power pins. The DIB applications that add relays make huge capacitors disconnect to remove the capacitor discharge time, which is generally known as the delay time or time constant of the RC circuit. In this paper, the authors propose a modified method without the DIB application increment (i.e., no relays) which they developed through a comparative analysis between the calculated settling time of the time constant of RC delay modeling and the actual settling time.

Integrating Automated Test Program Generation in Your Daily Workflow Saves Time (84)
As a follow-up to their TUG 2013 paper titled Automated Test Program Generation for Automotive Devices, the authors describe how the automated test program generator can support the complete complex process of test program development, including analyzing and assigning test system resources relevant to the device-related requirements. Using practical examples, they show how the tool can make life on the test floor easier for the user. The integrated checks within the tool are also described, including those that find potential conflicts and errors early in the development process, thus avoiding time- and cost-consuming corrective actions later.

Increasing Tester Resource Utilization Efficiency for Continuity Test to Reduce Test Time and System Resources (95)
The continuity test method measures diode voltage through forced current with PMU or DCVI. The power continuity test is a kind of continuity test and its test time is usually less than 10% of the total test time, even though a lot of settling time is required depending on the capacitor value with the traditional forced current and voltage measurement method. There is a trend in today's devices to increase the required number of pins to measure the power continuity and increase capacitance on each power pin continuously. The UltraVS256 is a high pin count voltage source and useful for reducing settling time and PPMU resources for power continuity test to set negative voltage. In this paper, the authors describe two test methods. They are: 1) negative voltage forcing and current measurement mode to reduce settling time and PMU resources and 2) negative voltage forcing and voltage measurement with current limiting to reduce PMU resources.

IG-XL Run-Time Error Processing: How Binning Is Determined for an Error (108)
Should an error occur while executing a test, IG-XL makes a bin assignment based on designated factors in the test program. Existence of a properly written errorHandler, complete flow table data, and the type of error all affect binning results. In this paper, the authors describe what constitutes an IG-XL run-time error and explain how IG-XL makes the binning decision. Understanding this behavior will ensure proper binning of devices when an error occurs.

Examining the Throughput Benefits of Distributed vs. Centralized Multicore Computing (109)
Faster throughput and parallel efficiency are achieved in a multi-process/multi-threaded environment utilizing multiple cores. In this paper, the authors examine the performance benefits of using multiple multicore computers such as the UltraFLEX distributed DSP system vs. an approach of running multiple threads on the tester computer. A multicore single computer handling both DSP and host computer functionality faces many disadvantages such as increased communication overhead as well as inadequate shared memory and cache per core that leads to increased test times. The advantages of using multiple multicore computer architecture for DSP computations are explored. Finally, the future DSP challenges and how the current UltraFLEX DSP architecture has been built to handle them are described.

Test List Generator for J750 (113)
A test list contains information about the flow and exact sequence as well as conditions such as test names, test numbers, binning information, limits, patterns, DC and AC setups and actual pin levels. This information is useful for validating the flow and ensuring that the correct conditions are set for all the tests. However, these data are usually generated manually by digging through the test program and going through each test one by one. This process is often tedious, time consuming and error-prone. In this paper, the author describes and shares the Test List Generator for J750, a tool that automates this task.

Modular Programming on the J750 (119)
As an alternative to Teradyne test templates or custom test templates, VBT functions can be used to keep the reusability up and development time down while greatly reducing test time. Functions can be written for product families and ease development while benefiting cost of test. In this paper, the authors show the results of a benchmark study where a program was taken out of templates and put into fewer than 10 custom VBT functions designed for the product family. This change resulted in significant test time savings while allowing a better code flow for this particular product family.

Visual Basic Dictionaries: Solve Your Software Interfacing Problems (124)
The Visual Basic (VB) Dictionary object can be a flexible and efficient tool for solving programming problems. In this paper, the authors describe two case studies that demonstrate how to use VB Dictionary effectively. Information can be read very quickly from an Excel worksheet during validation and used throughout the test program. One case describes how the dictionary creates an Excel worksheet device register interface which can be modified during run time throughout the program or interactively; and one case describes how it is implemented to manage limits, test names and measurement range information per test instance.

Measuring Low Noise RF Frequency Using FLEX HSD (128)
In this paper, the author proposes a method to test the phase-locked loop (PLL) output divider at frequencies up to 5GHz using the microFLEX. The measurement range is beyond DCTime and HSD400 bandwidth. In order to perform the test using the HSD frequency counter mode, the DUT output signal is first divided by a high-speed frequency divider IC on the DIB board. In this case, the DUT is an ultra low noise/jitter device. The method is carefully designed to minimize to additive jitter that could affect other test parameters. The pros and cons of using this on board solution, including DIB design considerations, test time and cost savings, are also included.

Leveraging a Code Library to Speed Inter-Platform Code Application (129)
In this paper, the authors propose, discuss and give examples of a library of Visual Basic functions that can equalize the instructions required to achieve specific goals on different tester platforms. Once the library is established (but always growing), main user code can be built on these "helper" functions to maximize program code portability from system to system. Examples that exhibit J750 to UltraFLEX parallels are included.

Associating High PTE and Resources Usage on ETS-800 for a Successful DIB Design (133)
The ETS-800 with the Multisite Sector Technology is designed for parallel test efficiency (PTE) greater than 99%. Getting this high PTE is part of the equation for building a successful multisite test application. Among the numerous factors in this equation is the architecture of the instrumentation itself that is part of the solution. In this paper, the author describes PTE and how it can be applied on the ETS-800 and navigates across each instrument. Some practical examples for associating high PTE and fully optimizing the usage of the instrumentation available is also included.

Getting the Most Out of the MST Environment: Tips & Techniques (139)
EagleVision Multi-Sector Technology (MST) on the ETS-800 platform, with its application-program development system based upon Microsoft’s® VisualStudio®2010, offers many features and a few challenges. In this paper, the author delves into some of the useful features of the system and suggests some development best practices to get the most from your coding and debug sessions on the ETS-800/MST platform. These techniques should help newcomers to the Eagle environment create useful and productive coding and debugging habits. They should also help veteran users of EagleVision and earlier versions of VisualStudio make a smooth transition into productive application-development under MST.

Getting a Head-Start on Converting IG-XL Programs into ETS-800 MST Programs (140)
It is expected that some programs from the FLEX and microFLEX IG-XL environment will need to be ported to the ETS-800 platform. In this paper, the author describes a tool that can help replicate the program structure of a FLEX/microFLEX application under EagleVision ‘MST, giving developers a good head start on their porting effort. Topics include formatting requirements for the IG-XL program as well as items that are supported or excluded from automated translation.